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FEMTOCLOCKTM CRYSTAL-TOLVDS/LVCMOS CLOCK GENERATOR
ICS8402010I
GENERAL DESCRIPTION
ICS8402010I is a low phase noise Clock Generator IC S and is a member of the HiperClockSTM family of high HiPerClockSTM performance clock solutions from IDT. The device provides three banks of outputs and a reference clock. Each bank can be independently enabled by using output enable pins. A 25MHz, 18pF parallel resonant crystal is used to generate the 16.66MHz, 62.5MHz and 25MHz frequencies. The typical RMS phase jitter for this device is less than 1ps.
FEATURES
* Three banks of outputs: Bank A/B: three single-ended LVCMOS outputs at 16.66MHz Bank C: three differential LVDS outputs at 62.5MHz One single-ended reference clock output at 25MHz * Crystal input frequency: 25MHz * Maximum output frequency: 62.5MHz * RMS phase jitter @ 62.5MHz, using a 25MHz crystal, Integration Range (1.875MHz - 20MHz): 0.375ps (typical) * Full 3.3V operating supply * -40C to 85C ambient operating temperature * Available in both standard (RoHS 5) and lead-free (RoHS6) packages
BLOCK DIAGRAM
OE[2:0] Pullup
3 LVCMOS - 16.66MHz
QA0 QA1 QA2
25MHz
/30
PIN ASSIGNMENT
XTAL_OUT XTAL_IN
XTAL_IN
LVCMOS - 16.66MHz
OSC
VDDA OE2 OE1 OE0 GND
GND
XTAL_OUT
Phase Detector
VCO
500MHz
QB0 QB1 QB2
/30
32 31 30 29 28 27 26 25 VDDO_REF REF_OUT GND GND QA0 QA1 QA2 VDDO_A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 24 23 VDDO_C nQC2 QC2 nQC1 QC1 nQC0 QC0 VDDO_C
/20
ICS8402010I
32-Lead VFQFN 5mm x 5mm x 0.925mm package body K Package Top View
LVDS 62.5MHz
22 21 20 19 18 17
QC0 nQC0
/8
QC1 nQC1 QC2 nQC2
LVCMOS - 25MHz
QB0
QB1
QB2
GND
MR
VDDO_B
GND
VDD
REF_OUT
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TABLE 1. PIN DESCRIPTIONS
Number 1 2 3, 4, 13, 16, 25, 32 5, 6, 7 8 9 10, 11, 12 14 15 17, 24 18, 19 20, 21 22, 23 26 Name VDDO_REF REF_OUT GND QA0, QA1, QA2 VDDO_A VDDO_B QB0, QB1, QB2 MR VDD VDDO_C QC0, nQC0 QC1, nQC1 QC2, nQC2 VDDA Power Output Power Output Power Power Output Input Power Power Output Output Output Power Type Description Output power supply pin for REF_OUT output. Single-ended reference clock output. LVCMOS/LVTTL interface levels. Power supply ground. Single-ended Bank A clock outputs. LVCMOS/LVTTL interface levels. Output power supply pin for Bank A LVCMOS outputs. Output power supply pin for Bank B LVCMOS outputs. Single-ended Bank B clock outputs. LVCMOS/LVTTL interface levels. Master reset, resets the internal dividers. During reset, LVCMOS outputs are pulled LOW and LVDS outputs are pulled LOW and Pulldown HIGH, (QCx pulled LOW, nQCx pulled HIGH). LVCMOS/LVTTL interface levels. Core supply pin. Output power supply pin for Bank C LVDS outputs. Differential Bank C clock outputs. LVDS interface levels. Differential Bank C clock outputs. LVDS interface levels. Differential Bank C clock outputs. LVDS interface levels. Analog supply pin.
Output enable pins. See Table 3. LVCMOS/LVTTL interface levels. 27, 28, 29 OE0, OE1, OE2 Input Pullup 30, XTAL_IN, Cr ystal oscillator interface. XTAL_OUT is the output. Input 31 XTAL_OUT XTAL_IN is the input. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN CPD RPULLUP RPULLDOWN ROUT Parameter Input Capacitance Power Dissipation Capacitance (per output) Input Pullup Resistor Input Pulldown Resistor Output Impedance QA[0:2], QB[0:2], REF_OUT QA[0:2], QB[0:2], REF_OUT VDD, VDDO_A = VDDO_B = VDDO_REF = 3.465V Test Conditions Minimum Typical 4 15 51 51 20 Maximum Units pF pF k k
TABLE 3. OE FUNCTION TABLE
Inputs OE2 X X X X 0 1 OE1 X X 0 1 X X OE0 0 1 X X X X Output States QA0, QB0, QC0 disabled QA0, QB0, QC0 enabled QA1, QB1, QC1 disabled QA1, QB1, QC1 enabled QA2, QB2, QC2 disabled QA2, QB2, QC2 enabled
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ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, IO (LVCMOS) Outputs, IO (LVDS, VDDO_C) Continuous Current Surge Current Operating Temperature Range, TA Storage Temperature, TSTG Package Thermal Impedance, JA Junction-to-Ambient Package Thermal Impedance, JB Junction-to-Board Package Thermal Impedance, JC Junction-to-Case 10mA 15mA -40C to +85C -65C to 150C 37.0C/W (0 mps) 0.5C/W 29.6C/W 4.6V -0.5V to VDD + 0.5V -0.5V to VDDO_A, _B + 0.5V NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO_A = VDDO_B = VDDO_REF = VDDO_C = 3.3V 5%,TA = -40C TO 85C
Symbol V DD VDDA VDDO_A, VDDO_B, VDDO_C, VDDO_REF I DD IDDA IDDO_A + IDDO_B + IDDO_C + IDDO_REF Parameter Core Supply Voltage Analog Supply Voltage Test Conditions Minimum 3.135 VDD - 0.15 3.135 Typical 3.3 3.3 Maximum 3.465 VDD 3.465 Units V V
Output Supply Voltage
3.3V
V
Power Supply Current Analog Supply Current Output Supply Current
25 15 30
mA mA mA
TABLE 3B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDO_A = VDDO_B = VDDO_REF = 3.3V 5%,TA = -40C TO 85C
Symbol Parameter VIH VIL IIH IIL VOH VOL Input High Voltage Input Low Voltage Input High Current Input Low Current Output High Voltage; NOTE 1 OE0, OE1, OE2 MR OE0, OE1, OE2 MR REF_OUT, QA[0:2], QB[0:2] VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V VDDO_X = 3.465V -150 -5 2.6 0.5 Test Conditions Minimum Typical 2 -0.3 Maximum VDD + 0.3 0.8 5 150 Units V V A A A A V V
Output REF_OUT, VDDO_X = 3.465V Low Voltage; NOTE 1 QA[0:2], QB[0:2] NOTE: VDDO_X denotes VDDO_A, VDDO_B and VDDO_REF. NOTE 1: Outputs terminated with 50 to VDDO_A, _B, _REF/2. See Parameter Measurement Information, Output Load Test Circuit diagram.
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TABLE 3C. LVDS DC CHARACTERISTICS, VDD = VDDO_C = 3.3V 5%,TA = -40C TO 85C
Symbol VOD VOD VOS VOS Parameter Differential Output Voltage VOD Magnitude Change Offset Voltage VOS Magnitude Change 1.325 1.450 Test Conditions Minimum 300 Typical 450 Maximum 550 50 1.575 50 Units mV mV V mV
TABLE 4. CRYSTAL CHARACTERISTICS
Parameter Mode of Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance Drive Level NOTE: Characterized using an 18pF parallel resonant cr ystal. Test Conditions Minimum Typical 25 50 7 1 Maximum Units MHz pF mW Fundamental
TABLE 5. AC CHARACTERISTICS, VDD = VDDO_A = VDDO_B = VDDO_REF = VDDO_C = 3.3V 5%,TA = -40C TO 85C
Symbol Parameter QC[0:2]/ nQC[0:2] REF_OUT QA[0:2], QB[0:2] QA[0:2], QB[0:2] QC[0:2]/ nQC[0:2] QA[0:2] Test Conditions Minimum Typical 62.5 25 16.66 125 60 100 125 Maximum Units MHz MHz MHz ps ps ps ps ps 450 1000 53 55 ps ps % %
fOUT
Output Frequency
tsk(o)
Output Skew; NOTE 1, 2 Bank Skew; NOTE 2, 3
tsk(b)
QB[0:2] RMS Phase Jitter QC[0:2]/ 62.5MHz, Integration Range: tjit(O) 0.375 (Random); NOTE 4 nQC[0:2] 1.875MHz - 20MHz QC[0:2]/ 20% to 80% 165 nQC[0:2] Output tR / tF Rise/Fall Time QA[0:2], 20% to 80% 450 QB[0:2] QC[0:2]/ 47 nQC[0:2] odc Output Duty Cycle QA[0:2], 45 QB[0:2] NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO_X/2. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Defined as skew within a bank of outputs at the same voltage and with equal load conditions. NOTE 4: Please refer to the Phase Noise Plot.
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TYPICAL PHASE NOISE AT 62.5MHZ (LVDS)
62.5MHz
RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.375ps (typical)
Ethernet Filter Phase Noise Result by adding Ethernet Filter to raw data OFFSET FREQUENCY (HZ)
5
NOISE POWER dBc Hz
Raw Phase Noise Data
IDT TM / ICSTM LVDS/LVCMOS CLOCK GENERATOR
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PARAMETER MEASUREMENT INFORMATION
1.65V5% 1.65V5% VDD, VDDO_A, VDDO_B, VDDO_REF
SCOPE
VDDA
Qx
SCOPE
3.3V5% POWER SUPPLY + Float GND -
VDD, VDDO_C VDDA
Qx
LVCMOS
LVDS
nQx
GND
-1.65V5%
3.3V LVDS OUTPUT LOAD AC TEST CIRCUIT
3.3V LVCMOS OUTPUT LOAD AC TEST CIRCUIT
Phase Noise Plot
V
Noise Power
DDO
Qx
2
Phase Noise Mask
Qy
V
DDO
2 tsk(o)
f1
Offset Frequency
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
RMS PHASE JITTER
LVCMOS OUTPUT SKEW
nQCx QCx nQCy QCy
QXy QXx
VDDO 2
VDDO 2 tsk(b)
tsk(b)
Where X = A or B
LVDS BANK SKEW
LVCMOS BANK SKEW
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PARAMETER MEASUREMENT INFORMATION, CONTINUED
V
DDO
nQC[0:2] QC[0:2]
QA[0:2], QB[0:2]
2
t PW
t
PERIOD
t PW
t
PERIOD
odc =
t PW t PERIOD
x 100%
odc =
t PW t PERIOD
x 100%
LVCMOS OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
LVDS OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
nQC[0:2]
80%
80% VOD
QA[0:2], QB[0:2], REF_OUT
20%
80%
80% 20%
QC[0:2]
20% tR tF
20% VOS GND
tR
tF
LVDS OUTPUT RISE/FALL TIME
LVCMOS OUTPUT RISE/FALL TIME
VDDO

VDDO
out
out
DC Input
100
VOD/ VOD out
out
VOS/ VOS
DIFFERENTIAL OUTPUT VOLTAGE SETUP
OFFSET VOLTAGE SETUP
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LVDS
DC Input
LVDS
ICS8402010I FEMTOCLOCKTM CRYSTAL-TO-LVDS/LVCMOS CLOCK GENERATOR
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The ICS8402010I provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA and VDDO_X should be individually connected to the power supply plane through vias, and 0.01F bypass capacitors should be used for each pin. Figure 1 illustrates this for a generic VCC pin and also shows that VDDA requires that an additional 10 resistor along with a 10F bypass capacitor be connected to the VDDA pin.
3.3V VDD .01F VDDA .01F 10F 10
FIGURE 1. POWER SUPPLY FILTERING
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS:
LVCMOS CONTROL PINS Control pins have internal pullups or pulldowns; additional resistance is not required but can be added for additional protection. A 1k resistor can be used.
OUTPUTS:
LVCMOS OUTPUTS All unused LVCMOS output can be left floating. There should be no trace attached. LVDS OUTPUTS All unused LVDS outputs should be terminated with 100 resistor between the differential pair.
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CRYSTAL INPUT INTERFACE
The ICS8402010I has been characterized with 18pF parallel resonant crystals. The capacitor values shown in Figure 2 below were determined using a 25MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error.
XTAL_IN C1 27p X1 18pF Parallel Crystal XTAL_OUT C2 27p
FIGURE 2. CRYSTAL INPUt INTERFACE
LVCMOS TO XTAL INTERFACE
The XTAL_IN input can accept a single-ended LVCMOS signal through an AC couple capacitor. A general interface diagram is shown in Figure 3. The XTAL_OUT pin can be left floating. The input edge rate can be as slow as 10ns. For LVCMOS inputs, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. This configuration requires that the output impedance of the driver
VDD
(Ro) plus the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50 applications, R1 and R2 can be 100. This can also be accomplished by removing R1 and making R2 50.
VDD
R1 Ro Rs Zo = 50 .1uf XTAL_IN
Zo = Ro + Rs
R2
XTAL_OUT
FIGURE 3. GENERAL DIAGRAM FOR LVCMOS DRIVER
TO
XTAL INPUT INTERFACE
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LVDS DRIVER TERMINATION
A general LVDS interface is shown in Figure 4. In a 100 differential transmission line environment, LVDS drivers require a matched load termination of 100 across near
3.3V LVDS_Driv er + R1 100
the receiver input. For a multiple LVDS outputs buffer, if only partial outputs are used, it is recommended to terminate the unused outputs.
3.3V
-
100 Ohm Differiential Transmission Line
FIGURE 4. TYPICAL LVDS DRIVER TERMINATION
VFQFN EPAD THERMAL RELEASE PATH
In order to maximize both the removal of heat from the package and the electrical performance, a land patter n must be incorporated on the Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in Figure 5. The solderable area on the PCB, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. Sufficient clearance should be designed on the PCB between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must be connected to ground through these vias. The vias act as "heat pipes". The number of vias (i.e. "heat pipes") are application specific and dependent upon the package power dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. It is recommended to use as many vias connected to ground as possible. It is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/ slug and the thermal land. Precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. Note: These recommendations are to be used as a guideline only. For further information, refer to the Application Note on the Surface Mount Assembly of Amkor's Thermally/ Electrically Enhance Leadfame Base Package, Amkor Technology.
PIN
SOLDER
EXPOSED HEAT SLUG
SOLDER
PIN
PIN PAD
GROUND PLANE THERMAL VIA
LAND PATTERN (GROUND PAD)
PIN PAD
FIGURE 5. P.C.ASSEMBLY FOR EXPOSED PAD THERMAL RELEASE PATH -SIDE VIEW (DRAWING NOT TO SCALE)
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POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8402010I. Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8402010I is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. Core and Output Power Dissipation
*
Power (core, output) = VDD_MAX * (IDD + IDDO_X + IDDA ) = 3.465V * (25mA + 30mA + 15mA) = 242.6mW
LVCMOS Output Power Dissipation
* * *
Output Impedance ROUT Power Dissipation due to Loading 50 to VDDO/2 Output Current IOUT = VDDO_MAX / [2 * (50 + ROUT)] = 3.465V / [2 * (50 + 20)] = 24.7mA Power Dissipation on the ROUT per LVCMOS output Power (ROUT) = ROUT * (IOUT)2 = 20 * (24.7mA)2 = 12.25mW per output Total Power Dissipation on the ROUT Total Power (ROUT) = 12.25mW * 6 = 73.5mW
Total Power Dissipation
*
Total Power = Power (core, output) + Power Dissipation (ROUT) = 242.6mW + 73.5mW = 316.1mW
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2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 37C/W per Table 6. Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 0.316W * 37C/W = 96.7C. This is below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board.
TABLE 6. THERMAL RESISTANCE JA FOR 32-LEAD VFQFN, FORCED CONVECTION
JA vs. Air Flow (Meters per Second)
0
Multi-Layer PCB, JEDEC Standard Test Boards 37.0C/W
1
32.4C/W
2.5
29.0C/W
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RELIABILITY INFORMATION
TABLE 7. JAVS. AIR FLOW TABLE
FOR
32 LEAD VFQFN
JA vs. Air Flow (Meters per Second)
0
Multi-Layer PCB, JEDEC Standard Test Boards 37.0C/W
1
32.4C/W
2.5
29.0C/W
TRANSISTOR COUNT
The transistor count for ICS8402010I is: 7782
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PACKAGE OUTLINE - K SUFFIX FOR 32 LEAD VFQFN
NOTE: The following package mechanical drawing is a generic drawing that applies to any pin count VFQFN package. This drawing is not intended to convey the actual pin count or pin layout of
this device. The pin count and pinout are shown on the front page. The package dimensions are in Table 8 below.
TABLE 7. PACKAGE DIMENSIONS
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS (VHHD -2/ -4) SYMBOL N A A1 A3 b e ND NE D, E D2, E2 L 3.0 0.30 0.18 0.50 BASIC 8 8 5.0 BASIC 3.3 0.50 0.80 0 0.25 Reference 0.30 Minimum 32 1. 0 0.05 Maximum
Reference Document: JEDEC Publication 95, MO-220
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TABLE 8. ORDERING INFORMATION
Part/Order Number 8402010AKI 8402010AKIT 8402010AKILF 8402010AKILFT Marking ICS402010AI ICS402010AI ICS02010AIL ICS02010AIL Package 32 Lead VFQFN 32 Lead VFQFN 32 Lead "Lead-Free" VFQFN 32 Lead "Lead-Free" VFQFN Shipping Packaging Tray 1000 Tape & Reel Tray 1000 Tape & Reel Temperature -40C to 85C -40C to 85C -40C to 85C -40C to 85C
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
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Corporate Headquarters
Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800-345-7015 (inside USA) +408-284-8200 (outside USA)
(c) 2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA

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